Overview

AMD Vitis HLS (High-Level Synthesis) enables developers to convert C/C++ functions into synthesizable RTL (register-transfer level) code for use on AMD adaptive SoCs and FPGAs. It integrates with the Vitis unified software platform and the Vivado design flow, allowing export as Vivado IP or Vitis kernels for heterogeneous designs. Vitis HLS provides simulation, synthesis, code analysis and pragmas to optimize performance, area, and interfaces — helping software-oriented developers produce hardware-optimized kernels while keeping the flow aligned with system-level toolchains and documentation.

Features and Capabilities

• High-Level Synthesis Core: Converts C/C++ into RTL automatically for FPGA implementation; supports export as Vivado IP or Vitis kernel for the PL region.
• Integration with Vitis & Vivado: Tight integration with the Vitis unified IDE and Vivado toolchain for a seamless software-to-hardware flow and downstream place-and-route.
• Code Analysis & Pragmas: Includes a code analyzer and pragmas to guide loop unrolling, pipelining, interface generation and resource directives for performance/area trade-offs.
• Simulation & Verification: Support for C simulation, co-simulation and waveform inspection to validate functional correctness before RTL export.
• Optimization Guidance: Provides reports and metrics (latency, II, resources) so developers can iteratively tune kernels for throughput and utilization.
• Tutorials & Examples: Official tutorials, labs and example repositories to accelerate onboarding and show common kernel patterns.
• Standards & Interfaces: Built-in patterns and templates for AXI4/AXI4-Lite/AXI-Stream interfaces to integrate with system-level designs.
• Export Options: Export as a Vivado IP ZIP or a Vitis kernel (.xo) enabling either RTL-based flows or heterogeneous acceleration flows.
• Documentation & Guides: Extensive user guide, programmers’ guide and release-specific notes to support advanced usage and best practices.