The toolbox includes reference applications to demonstrate the development of complex subsystems. You can model, explore, and simulate DSP algorithm hardware architectures, assessing trade-offs in resource usage, power, and GSPS throughput with support for serial and parallel processing. The interactive DSP HDL IP Designer app lets you customize input stimulus and configure ports and properties of DSP algorithms directly. You can generate readable, synthesizable code from the algorithms in VHDL® and Verilog® (with HDL Coder) and SystemVerilog DPI verification components (with HDL Verifier).